| Day | 09:30-10:30 | 10:30-11:30 | 11:30-11:50 | 11:50-12:50 | 12:50-01:30 | 01:30-02:30 | 02:30-03:30 | 03:30-04:30 |
|---|---|---|---|---|---|---|---|---|
| Mon | CMOS DICD | FPGA A&A | BREAK | LPVLSID | LUNCH | CMOS DIC LAB | ||
| Tue | MC&PDSP | LPVLSID | BREAK | RM&IPR | LUNCH | CMOS DICD | FPGA A&A | DM |
| Wed | LPVLSID | MC&PDSP | BREAK | DM | LUNCH | MC&PDSP LAB | ||
| Thu | FPGA A&A | CMOS DICD | BREAK | RM&IPR | LUNCH | RTL SYNTHESIS & VERIFICATION | ||